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LTC2757 18-Bit SoftSpan IOUT DAC with Parallel I/O FEATURES
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DESCRIPTION
The LTC(R)2757 is an 18-bit multiplying parallel-input, current-output digital-to-analog converter that provides full 18bit performance--INL and DNL of 1LSB maximum--over temperature without any adjustments. 18-bit monotonicity is guaranteed in all performance grades. This SoftSpanTM DAC operates from a single 3V to 5V supply and offers six output ranges (up to 10V) that can be programmed through the parallel interface or pin-strapped for operation in a single range. In addition to its precision DC specifications, the LTC2757 also offers excellent AC specifications, including 2.1s full-scale settling to 1LSB and 1.4nV*s glitch impulse. The LTC2757 uses a bidirectional input/output parallel interface that allows readback of any on-chip register, including DAC output-range settings; and a CLR pin and power-on reset circuit that each reset the DAC output to 0V regardless of output range.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. SoftSpan is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Maximum 18-Bit INL Error: 1 LSB Over Temperature Program or Pin-Strap Six Output Ranges: 0V to 5V, 0V to 10V, -2.5V to 7.5V, 2.5V, 5V, 10V Guaranteed Monotonic Over Temperature Low Glitch Impulse 1.4nV*s (3V), 3nV*s (5V) 18-Bit Settling Time: 2.1s 2.7V to 5.5V Single Supply Operation Reference Current Constant for All Codes Voltage-Controlled Offset and Gain Trims Parallel Interface with Readback of All Registers Clear and Power-On-Reset to 0V Regardless of Output Range 48-Pin 7mm x 7mm LQFP Package
APPLICATIONS
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Instrumentation Medical Devices Automatic Test Equipment Process Control and Industrial Automation
TYPICAL APPLICATION
18-Bit Voltage Output DAC with Software-Selectable Ranges
REF 5V 1.0
LTC2757 Integral Nonlinearity
10V RANGE 0.8
+
LT1012
0.6 0.4 INL (LSB) 27pF IOUT1 150pF 0.2 0 -0.2 -0.4 -0.6 90C 25C -45C 0 65536 131072 CODE 196608 262143
2757 TA01b
-
RIN
RCOM
REF
ROFS
RFB
WR UPD READ D/S CLR
WR UPD READ D/S CLR M-SPAN GAIN ADJUST
LTC2757 18-BIT DAC WITH SPAN SELECT
GND VDD 0.1F
2757 TA01
GEADJ SPAN I/O S2-S0 DATA I/O D17-D0
VOSADJ
OFFSET ADJUST
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+
5V
IOUT2
-
LT1468 VOUT
-0.8 -1.0
1
LTC2757 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
PIN CONFIGURATION
TOP VIEW GEADJ RCOM REF REF ROFS ROFS RFB RFB IOUT1 VOSADJ S1 S0 48 47 46 45 44 43 42 41 40 39 38 37
IOUT1, IOUT2, RCOM to GND .....................................0.3V RFB, ROFS, RIN, REF, VOSADJ, GEADJ to GND ........... 15V VDD to GND .................................................. -0.3V to 7V S2, S1, S0, D17-D0 to GND ............... -0.3V to VDD + 0.3V (7V Max) WR, UPD, D/S, READ, M-SPAN, CLR to GND .................................. -0.3V to 7V Operating Temperature Range LTC2757C .................................................... 0C to 70C LTC2757I..................................................-40C to 85C Maximum Junction Temperature .......................... 150C Storage Temperature Range .................. -65C to 150C Lead Temperature (Soldering, 10 sec)................... 300C
1 2 3 4 IOUT2S 5 IOUT2F 6 GND 7 D17 8 D16 9 D15 10 D14 11 D13 12 RIN RIN S2 GND
36 35 34 33 32 31 30 29 28 27 26 25
WR UPD READ D/S DNC D0 D1 D2 D3 D4 D5 D6
LX PACKAGE 48-LEAD (7mm 7mm) PLASTIC LQFP TJMAX = 150C, JA = 53C/W
ORDER INFORMATION
LEAD FREE FINISH LTC2757BCLX#PBF LTC2757BILX#PBF LTC2757ACLX#PBF LTC2757AILX#PBF PART MARKING* LTC2757LX LTC2757LX LTC2757LX LTC2757LX PACKAGE DESCRIPTION 48-Lead (7mm x 7mm) Plastic LQFP 48-Lead (7mm x 7mm) Plastic LQFP 48-Lead (7mm x 7mm) Plastic LQFP 48-Lead (7mm x 7mm) Plastic LQFP TEMPERATURE RANGE 0C to 70C -40C to 85C 0C to 70C -40C to 85C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on non-standard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
D12 13 D11 14 D10 15 D9 16 VDD 17 GND 18 GND 19 CLR 20 M-SPAN 21 DNC 22 D8 23 D7 24
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LTC2757 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Resolution Monotonicity DNL INL GE GETC BZE BZSTC PSR ILKG Differential Nonlinearity Integral Nonlinearity Gain Error Gain Error Temperature Coefficient Bipolar Zero Error Bipolar Zero Temperature Coefficient Power Supply Rejection IOUT1 Leakage Current GEADJ: 0V, All Output Ranges (Note 3) All Bipolar Ranges (Note 3) VDD = 5V, 10% VDD = 3V, 10% TA = 25C TMIN to TMAX
l l l l
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
LTC2757B CONDITIONS
l l l l l
LTC2757A MAX MIN 18 18 1 2 48 0.4 0.4 5 0.25 36 3 0.15 1.6 4 0.15 0.4 0.05 0.8 2 2 5 24 1 1 32 TYP MAX UNITS Bits Bits LSB LSB LSB ppm/C LSB ppm/C LSB/V nA
MIN 18 18
TYP
Static Performance
0.25 0.15
0.05
2 5
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL Analog Pins R1, R2 RREF RFB ROFS RVOSADJ RGEADJ CIOUT1 Reference Inverting Resistors DAC Input Resistance Feedback Resistor Bipolar Offset Resistor Offset Adjust Resistor Gain Adjust Resistor Output Capacitance Full-Scale Zero-Scale Span Code = 000, 10V Step (Note 7) To 0.0004% FS VDD = 5V (Note 8) VDD = 3V (Note 8) VDD = 5V (Note 9) VDD = 3V (Note 9) 0V to 5V Range, Code = Full-Scale, -3dB Bandwidth 0V to 5V Range, VREF = 10V, 10kHz Sine Wave (Note 10) Multiplying (Note 11) at IOUT1 (Note 4) (Note 5) (Note 6) (Note 6)
l l l l l l
PARAMETER
CONDITIONS
MIN 16 8 8 16 1024 2048
TYP 20 10 10 20 1280 2560 90 40 2.1 3 1.4 4 1.8 1 0.4 -110 13
MAX
UNITS k k k k k k pF pF s nV*s nV*s nV*s nV*s MHz mV dB nV/Hz
Dynamic Performance Output Settling Time Glitch Impulse Digital-to-Analog Glitch Impulse Reference Multiplying Bandwidth Multiplying Feedthrough Error THD Total Harmonic Distortion Output Noise Voltage Density
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LTC2757 ELECTRICAL CHARACTERISTICS
SYMBOL VDD IDD VIH VIL PARAMETER Supply Voltage Supply Current, VDD Digital Input High Voltage Digital Input Low Voltage Hysteresis Voltage IIN CIN VOH VOL Digital Input Current Digital Input Capacitance IOH = 200A IOL = 200A VIN = GND to VDD VIN = 0V (Note 12)
l l l l
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C.
CONDITIONS
l
MIN 2.7
TYP
MAX 5.5
UNITS V A V V
Power Supply Digital Inputs = 0V or VDD 3.3V VDD 5.5V 2.7V VDD < 3.3V 4.5V < VDD 5.5V 2.7V VDD 4.5V
l l l l l
0.5 2.4 2
1
Digital Inputs
0.8 0.6 0.1 1 6 VDD - 0.4 0.4
V V V A pF V V
Digital Outputs
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS VDD = 4.5V to 5.5V Write and Update Timing t1 t2 t3 t4 t5 t6 t7 t8 t13 t14 t15 t17 t18 t19 t20 t22 t23 t24 I/O Valid to WR Rising Edge Set-Up I/O Valid to WR Rising Edge Hold WR Pulse Width UPD Pulse Width UPD Falling Edge to WR Falling Edge WR Rising Edge to UPD Rising Edge D/S Valid to WR Falling Edge Set-Up Time WR Rising Edge to D/S Valid Hold Time WR Rising Edge to READ Rising Edge READ Falling Edge to WR Falling Edge READ Rising Edge to I/O Propagation Delay UPD Valid to I/O Propagation Delay D/S Valid to READ Rising Edge READ Rising Edge to UPD Rising Edge UPD Falling Edge to READ Falling Edge READ Falling Edge to UPD Rising Edge I/O Bus Hi-Z to READ Rising Edge READ Falling Edge to I/O Bus Active (Note 12) CL = 10pF CL = 10pF (Note 12) No Update No Update (Note 12) (Note 12) (Note 12) No Data Shoot-Through (Note 12)
l l l l l l l l l l l l l l l l l l
TIMING CHARACTERISTICS
9 9 20 20 0 0 9 9 9 20 30 30 9 9 9 9 0 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Readback Timing
4
LTC2757 TIMING CHARACTERISTICS
SYMBOL CLR Timing t25 CLR Pulse Width Low
l
VDD = 5V, V(RIN) = 5V unless otherwise specified. The l denotes specifications that apply over the full operating temperature range, otherwise specifications are at TA = 25C.
PARAMETER CONDITIONS MIN 20 TYP MAX UNITS ns
VDD = 2.7V to 3.3V Write and Update Timing t1 t2 t3 t4 t5 t6 t7 t8 t13 t14 t15 t17 t18 t19 t20 t22 t23 t24 CLR Timing t25 CLR Pulse Width Low
l
I/O Valid to WR Rising Edge Set-Up I/O Valid to WR Rising Edge Hold WR Pulse Width UPD Pulse Width UPD Falling Edge to WR Falling Edge WR Rising Edge to UPD Rising Edge D/S Valid to WR Falling Edge Set-Up Time WR Rising Edge to D/S Valid Hold Time WR Rising Edge to Read Rising Edge Read Falling Edge to WR Falling Edge Read Rising Edge to I/O Propagation Delay UPD Valid to I/O Propagation Delay D/S Valid to Read Rising Edge Read Rising Edge to UPD Rising Edge UPD Falling Edge to Read Falling Edge READ Falling Edge to UPD Rising Edge I/O Bus Hi-Z to Read Rising Edge Read Falling Edge to I/O Bus Active (Note 12) CL = 10pF CL = 10pF (Note 12) No Update No Update (Note 12) (Note 12) (Note 12) No Data Shoot-Through (Note 12)
l l l l l l l l l l l l l l l l l l
18 18 30 30 0 0 18 18 18 40 48 48 18 9 9 18 0 40 30
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Readback Timing
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: Continuous operation above the specified maximum operating junction temperature may impair device reliability. Note 3: Temperature Coefficient is calculated by dividing the maximum change in the parameter by the specified temperature range. Note 4: R1 is measured from RIN to RCOM ; R2 is measured from REF to RCOM . Note 5: Parallel combination of the resistances from REF to IOUT1 and from REF to IOUT2. DAC input resistance is independent of code. Note 6: Because of the proprietary SoftSpan switching architecture, the measured resistance looking into each of the specified pins is constant for all output ranges if the IOUT1 and IOUT2 pins are held at ground.
Note 7: Using LT1468 with CFEEDBACK = 27pF A 0.0004% settling time . of 1.8s can be achieved by optimizing the time constant on an individual basis. See Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC. Note 8: Measured at the major carry transition, 0V to 5V range. Output amplifier: LT1468; CFB = 50pF . Note 9: Zero-code to full-code transition; REF = 0V. Falling transition is similar or better. Note 10: REF = 6VRMS at 1kHz. 0V to 5V range. DAC code = FS. Output amplifier = LT1468. Note 11: Calculation from Vn = 4kTRB, where k = 1.38E-23 J/K (Boltzmann constant), R = resistance (), T = temperature (K), and B = bandwidth (Hz). Note 12: Guaranteed by design. Not production tested.
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LTC2757 TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 5V, V(RIN) = 5V, TA = 25C, unless otherwise noted. Integral Nonlinearity (INL)
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 65536 131072 CODE 196608 262143
2757 G01
Differential Nonlinearity (DNL)
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 65536 131072 CODE 196608 262143
2757 G02
INL vs Output Range
1.0 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -2.5V -2.5V TO TO 2.5V 7.5V 0V -5V 0V TO TO TO 5V 5V 10V OUTPUT RANGE -10V TO 10V
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10V RANGE
10V RANGE
INL vs Temperature
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 85
2757 G04
DNL vs Temperature
1.0 0.8 0.6 +INL DNL (LSB) 0.4 GE (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -40 -20 0 20 40 TEMPERATURE (C) 60 80 85
2757 G05
Gain Error vs Temperature
16 12 8 10V 5V 2.5V TO 7.5V 0.25ppm/C TYP
0V TO 10V RANGE
0V TO 10V RANGE
+DNL
4 0 -4
-INL
-DNL -8 -12 -16 -40
2.5V
0V TO 5V
0V TO 10V
-20
40 0 20 TEMPERATURE (C)
60
80 85
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Bipolar Zero Error vs Temperature
16 12 8 BZE (LSB) 4 0 -4 -8 -12 -16 -40 -20 40 0 20 TEMPERATURE (C) 60 80 85
2757 G07
INL vs Reference Voltage
1.0 0.8 5V RANGE 1.0 0.8 0.6 +INL +INL DNL (LSB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 4 6 8 10
DNL vs Reference Voltage
5V RANGE
0.15ppm/C TYP 2.5V 5V INL (LSB)
0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 -10 -8 -6 -4 -2 0 2 V(RIN) (V) -INL -INL
+DNL
+DNL
10V
-2.5V TO 7.5V
-DNL
-DNL
-1.0 -10 -8 -6 -4 -2 0 2 V(RIN) (V)
4
6
8
10
2757 G08
2757 G09
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LTC2757 TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 5V, V(RIN) = 5V, TA = 25C, unless otherwise noted. INL vs VDD
1.0 0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3 3.5 4.5 4 V(RIN) (V) 5 5.5
2757 G10
DNL vs VDD
1.0 0.8 +INL 0.6 ATTENUATION (dB) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3 3.5 4.5 4 V(RIN) (V) 5 5.5
2757 G11
Multiplying Frequency Response vs Digital Code
0 -20 -40 -60 -80 -100 -120
ALL BITS OFF ALL BITS ON D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
10V RANGE
10V RANGE
+DNL
-INL
-DNL
-140 100
0V TO 5V OUTPUT RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 15pF 10k 100k FREQUENCY (Hz) 1M 10M
2757 G12
1k
Settling Full-Scale Step
Mid-Scale Glitch (VDD = 3V)
1.4nV*s TYP
Mid-Scale Glitch (VDD = 5V)
3nV*s TYP UPD 5V/DIV
UPD 5V/DIV
UPD 5V/DIV
GATED SETTLING WAVEFORM 100V/DIV (AVERAGED) 500ns/DIV LT1468 AMP; CFEEDBACK = 20pF 0V TO 10V STEP VREF = -10V; SPAN CODE = 000 tSETTLE = 1.8s to 0.0004% (18 BITS)
2757 G13
VOUT 10mV/DIV 500ns/DIV
2757 G14
VOUT 10mV/DIV 500ns/DIV
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0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER.
0V TO 5V RANGE LT1468 OUTPUT AMPLIFIER CFEEDBACK = 50pF RISING MAJOR CARRY TRANSITION. FALLING TRANSITION IS SIMILAR OR BETTER.
Supply Current vs Logic Input Voltage
12 10 8 IDD (mA) VDD = 5V 6 4 2 0 0 1 2 3 LOGIC VOLTAGE (V) 4
2757 G16
Logic Threshold vs Supply Voltage
2 1.75 1.5 1.25 FALLING 1 0.75 SUPPLY CURRENT (A) LOGIC THRESHOLD (V) 100 1000
Supply Current vs Update Frequency
ALTERNATING ZERO-SCALE/FULL-SCALE
ALL DIGITAL PINS TIED TOGETHER (EXCEPT READ TIED TO GND)
RISING
10
1 VDD = 5V VDD = 3V
VDD = 3V 0.5 5 2.5 3 3.5 4 4.5 VDD (V) 5 5.5
2757 G17
0.1
10
100
10k 100k 1k UPD FREQUENCY (Hz)
1M
2757 G18
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LTC2757 PIN FUNCTIONS
RIN (Pins 1, 2): Input Resistor for External Reference Inverting Amplifier. Normally tied to the external reference voltage. Typically 5V; accepts up to 15V. These pins are internally shorted together. S2 (Pin 3): Span I/O Bit 2. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. See Table 2. GND (Pins 4, 7, 18, 19): Ground. Tie to ground. IOUT2S, IOUT2F (Pins 5, 6): DAC Output Current Complement Sense and Force Pins. Tie to ground via a clean, low-impedance path. These pins may also be used with a precision ground buffer amp as a Kelvin sensing pair (see the Typical Applications section). D17-D9 (Pins 8-16): DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D17 (Pin 8) is the MSB. VDD (Pin 17): Positive Supply Input. 2.7V VDD 5.5V. Requires a 0.1F bypass capacitor to GND. CLR (Pin 20): Asynchronous Clear Input. When CLR is asserted low, the DAC output resets to VOUT = 0V. The LTC2757 selects the appropriate reset code according to the active output range--zero-scale for 0V to 5V and 0V to 10V spans, half scale for 2.5V, 5V and 10V spans, or quarter scale for -2.5V to 7.5V span. M-SPAN (Pin 21): Manual Span Control Input. M-SPAN can be pin-strapped to configure the LTC2757 for operation in a single, fixed output range. To configure the part for single-span use, tie M-SPAN directly to VDD. The output range is then set via hardware pin strapping; and the Span I/O port ignores Write, Update and Read commands. If M-SPAN is instead connected to ground (SoftSpan configuration), the output ranges are set and verified by using Write, Update and Read operations. See Manual Span Configuration in the Operation section. M-SPAN must be connected either directly to GND (for SoftSpan operation) or VDD (for single-span operation). DNC (Pins 22, 32): Do Not Connect. D8-D0 (Pins 23-31): DAC Input/Output Data Bits. These I/O pins set and read back the DAC code. D0 is the LSB. D/S (Pin 33): Data/Span Select Input. This pin is used to select activation of the Data (D/S = 0) or Span (D/S = 1) Input I/O pins (D0 to D17 or S0 to S2, respectively), along with their respective dedicated registers, for Write or Read operations. Update operations are unaffected by D/S, since all updates affect both Data and Span registers. For single-span operation, tie D/S to GND. READ (Pin 34): Read Input. When READ is asserted high, the Data I/O pins (D0-D17) or Span I/O pins (S0-S2) output the contents of a selected Input or DAC register (see Table 1). Data/Span ports are selected for readback with the D/S pin; the Input/DAC registers within those ports are selected for readback with the UPD pin. The readback function of the Span I/O pins is disabled when M-SPAN is tied to VDD. UPD (Pin 35): Update/Register Select Input. READ = low: Update function. When UPD is asserted high, the contents of the Input registers are copied into their respective DAC registers. The output of the DAC is updated, reflecting the new DAC register values. READ = high: Register selector function. The Update function is disabled and the UPD pin functions as a register selector. UPD = low selects Input registers for readback, high selects DAC registers. See Readback in the Operation section. WR (Pin 36): Active-Low Write Input. A Write operation copies the data present on the Data or Span I/O pins (D0D17 or S0-S2, respectively) into the Input register. The Write function is disabled when READ is high. S0 (Pin 37): Span I/O Bit 0. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. See Table 2. S1 (Pin 38): Span I/O Bit 1. Pins S0, S1 and S2 are used to program and to read back the output range of the DAC. See Table 2.
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LTC2757 PIN FUNCTIONS
VOSADJ (Pin 39): DAC Offset Adjust Pin. This voltage-control pin can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used. IOUT1 (Pin 40): DAC current output; normally tied to the negative input (summing junction) of the I/V converter amplifier. RFB (Pins 41, 42): DAC Feedback Resistor. Normally tied to the output of the I/V converter amplifier. The DAC output current from IOUT1 flows through the feedback resistor to the RFB pins. These pins are internally shorted together. ROFS (Pins 43, 44): Bipolar Offset Network. These pins provide the translation of the output voltage range for bipolar spans. Accepts up to 15V; normally tied to the positive reference voltage. These pins are internally shorted together. REF (Pins 45, 46): Feedback Resistor for the Reference Inverting Amplifier, and Reference Input for the DAC. Normally tied to the output of the reference inverting amplifier. Typically -5V; accepts up to 15V. These pins are internally shorted together. . RCOM (Pin 47): Center Tap Point of RIN and REF Normally tied to the negative input of the external reference inverting amplifier. GEADJ (Pin 48): Gain Adjust Pin. This voltage-control pin can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range. See System Offset and Gain Adjustments in the Operation section. Tie to ground if not used.
BLOCK DIAGRAM
48 GEADJ 2.56M R1 20k R2 20k VOSADJ IOUT1 18-BIT DAC WITH SPAN SELECT 3 18 IOUT2F IOUT2S 47 RCOM REF 45, 46 ROFS 43, 44 RFB 41, 42
RIN 1, 2 36 35 34 33 20 21 WR UPD READ D/S CLR
39 40 6 5
CONTROL LOGIC
DAC REGISTER 3
DAC REGISTER 18
M-SPAN
INPUT REGISTER
INPUT REGISTER
I/O PORT 3 3, 37, 38 SPAN I/O S2-S0
I/O PORT 18 8-16, 23-31 DATA I/O D17-D0
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LTC2757 TIMING DIAGRAMS
Write, Update and Clear Timing
t3 t1 WR t2
I/O INPUT t5 UPD
VALID t6
t7 D/S VALID
t4 t8
CLR
t25
2757 TD01
Readback Timing
READ WR t13 t14
t23 I/O INPUT t15 I/O OUTPUT VALID t17 t20 t19 UPD t18 D/S VALID t22 VALID
t24
2757 TD02
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LTC2757 OPERATION
Output Ranges The LTC2757 is a current-output, parallel-input precision multiplying DAC offering 1LSB INL and DNL over six software-selectable output ranges. Ranges can either be programmed in software for maximum flexibility or hardwired through pin-strapping. Two unipolar ranges are available (0V to 5V and 0V to 10V), and four bipolar ranges (2.5V, 5V, 10V and -2.5V to 7.5V). These ranges are obtained when an external precision 5V reference is used. The output ranges for other reference voltages are easy to calculate by observing that each range is a multiple of the external reference voltage. The ranges can then be expressed: 0 to 1x, 0 to 2x, 0.5x, 1x, 2x, and -0.5x to 1.5x. Digital Section The LTC2757 has four internal interface registers (see Block Diagram). Two of these--one Input and one DAC register--are dedicated to the Data I/O port, and two to the Span I/O port. Each port is thus double buffered. Double buffering provides the capability to simultaneously update the Span and Code registers, which allows smooth voltage transitions when changing output ranges. It also permits the simultaneous updating of multiple DACs or other parts on the data bus. Write and Update Operations Load the data input register directly from an 18-bit bus by holding the D/S pin low and then pulsing the WR pin low (Write operation). Load the Span Input register by holding the D/S pin high and then pulsing the WR pin low (Write operation). The Span and Data register structures are the same except for the number of parallel bits--the Span registers have three bits, while the Data registers have 18 bits. The DAC registers are loaded by pulsing the UPD pin high (Update operation), which copies the data held in the Input registers of both ports into the DAC registers. Note that Update operations always include both Data and Span registers; but the DAC register values will not change unless the Input register values have previously been changed by a Write operation. To make both registers transparent for flowthrough mode, tie WR low and UPD high. However, this defeats the deglitcher operation and output glitch impulse may increase. The deglitcher is activated on the rising edge of the UPD pin. The interface also allows the use of the Input and DAC registers in a master-slave, or edge-triggered, configuration. This mode of operation occurs when WR and UPD are tied together and driven by a single clock signal. The data bits are loaded into the Input register on the falling edge of the clock and then loaded into the DAC register on the rising edge. It is possible to control both ports on one 18-bit wide data bus by allowing Span pins S2 to S0 to share bus lines with the Data LSBs (D2 to D0). No Write or Read operation acts on both span and data, so there cannot be a signal conflict. The asynchronous clear pin (CLR) resets the LTC2757 to 0V (zero-, half- or quarter-scale code) in any output range. CLR resets both the Input and DAC data registers, but leaves the Span registers unchanged. The device also has a power-on reset that initializes the DAC to VOUT = 0V in any output range. The DAC powers up in the 0V to 5V range at zero-scale if the part is in SoftSpan configuration. For manual span (M-SPAN tied to VDD; see Manual Span Configuration), the DACs power-up in the manually-chosen range at the appropriate code. Manual Span Configuration Multiple output ranges are not needed in some applications. To configure the LTC2757 for single-span operation, tie the M-SPAN pin to VDD and the D/S pin to GND. The desired output range is programmed by tying S0, S1 and S2 to GND or VDD (see Figure 1 and Table 2). In this configuration, no range-setting software routine is needed; the part will initialize to the chosen output range at power-up, with VOUT = 0V. When configured for manual span operation, Span port readback is disabled.
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11
LTC2757 OPERATION
Readback The contents of any one of the four interface registers can be read back from the I/O ports by using the READ pin in conjunction with the D/S and UPD pins. The I/O pins and registers are grouped into two ports--Data and Span. The Data I/O port consists of pins D0-D17, and the Span I/O port consists of pins S0, S1 and S2. Each I/O port has one dedicated Input register and one dedicated DAC register. The register structure is shown in the Block Diagram. A Readback operation is initiated by asserting READ to logic high after selecting the desired I/O port. Select the I/O port (Data or Span) to be read back with the D/S pin. The selected I/O port's pins become logic outputs during readback, while the unselected I/O port's pins remain high-impedance digital inputs. With the I/O port selected, assert READ high and select the desired Input or DAC register using the UPD pin. Note that UPD is a two function pin--the Update function is only available when READ is low. If READ is high, the Update function is disabled and the UPD pin instead functions as a register selector, selecting an Input or DAC register for readback. Table 1 shows the readback functions for the LTC2757.
Table 1. Write, Update and Read Functions
READ D/S 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 WR UPD 0 0 1 1 0 0 1 1 X X X X 0 1 0 1 0 1 0 1 0 1 0 1 SPAN I/O Update DAC Register Write to Input Register Write/Update (Transparent) Update DAC register Read Input Register Read DAC Register DATA I/O Write to Input Register Write/Update (Transparent) Update DAC Register 2757 F01
The most common readback task is to check the contents of an Input register after writing to it, and before updating the new data to the DAC register. To do this, hold UPD low and assert READ high. The contents of the selected port's Input register are output to its I/O pins. To read back the contents of a DAC register, hold UPD low and assert READ high, then bring UPD high to select the DAC register. The contents of the selected DAC register are output by the selected port's I/O pins. Note: if no update is desired after the readback operation, UPD must be returned low before bringing READ low, otherwise the UPD pin will revert to its primary function and update the DAC.
Table 2. Span Codes
S2 0 0 0 0 1 1 S1 0 0 1 1 0 0 S0 0 1 0 1 0 1 SPAN Unipolar 0V to 5V Unipolar 0V to 10V Bipolar -5V to 5V Bipolar -10V to 10V Bipolar -2.5V to 2.5V Bipolar -2.5V to 7.5V
Codes not shown are reserved and should not be used.
VDD
M-SPAN S2 S1 S0 D/S WR
VDD LTC2757
UPD
READ 18 DATA I/O
Figure 1. Configuring the LTC2757 for Single-Span Operation (10V Range)
System Offset and Gain Adjustments
Update DAC Register Read Input Register Read DAC Register -
Many systems require compensation for overall system offset. This may be an order of magnitude or more greater than the offset of the LTC2757, which is so low as to be dominated by external output amplifier errors even when using the most precise op amps.
X = Don't Care
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12
LTC2757 OPERATION
The offset adjust pin VOSADJ can be used to null unipolar offset or bipolar zero error. The offset change expressed in LSB is the same for any output range: -V(VOSADJ ) VOS [LSB] = * 2048 V(RIN ) A 5V control voltage applied to VOSADJ produces VOS = -2048 LSB in any output range, assuming a 5V reference voltage at RIN. In voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (These functions hold regardless of reference voltage.) VOS = -(1/128)VOSADJ VOS = -(1/64)VOSADJ VOS = -(1/32)VOSADJ [0V to 5V, 2.5V spans] [0V to 10V, 5V, -2.5V to 7.5V spans] [10V span] The gain-error delta is non-inverting for positive reference voltages. Note that this pin compensates the gain by altering the inverted reference voltage V(REF). In voltage terms, the V(REF) delta is inverted and attenuated by a factor of 128. V(REF) = -(1/128)GEADJ The nominal input range of these pins is 5V; other voltages of up to 15V may be used if needed. However, do not use voltages divided down from power supplies; reference-quality, low-noise inputs are required to maintain the best DAC performance. The VOSADJ pin has an input impedance of 1.28M. This pin should be driven with a Thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2757. It should be shorted to GND if not used. The GEADJ pin has an input impedance of 2.56M, and is intended for use with fixed reference voltages only. It should be shorted to GND if not used.
The gain error adjust pin GEADJ can be used to null gain error or to compensate for reference errors. The gain error change expressed in LSB is the same for any output range: V(GE ADJ ) GE = * 2048 V(RIN )
OPERATION--EXAMPLES
1. Load 5V range with the output at 0V. Note that since span and code are updated together, the output, if started at 0V, will stay there. The 18-bit DAC code is shown in hex for compactness.
WR
SPAN I/O INPUT DATA I/O INPUT
010
20000H
UPD UPDATE (5V RANGE, VOUT = 0V) D/S READ = LOW VOUT 0V (00000H IN 0V to 5V RANGE) 0V (20000H IN 5V RANGE)
2757 TD03
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13
LTC2757 OPERATION--EXAMPLES
2. Load 10V range with the output at 5V, changing to -5V.
WR
SPAN I/O INPUT DATA I/O INPUT
011
30000H
10000H
UPD
UPDATE (5V)
UPDATE (-5V)
D/S READ = LOW +5V VOUT 0V -5V
2757 TD04
3. Write and update mid-scale code in 0V to 5V range (VOUT = 2.5V) using readback to check the contents of the input and DAC registers before updating.
WR
DATA I/O INPUT DATA I/O HI-Z OUTPUT
20000H
HI-Z
20000H INPUT REGISTER
00000H DAC REGISTER
UPD D/S
UPDATE (2.5V)
READ +2.5V VOUT 0V
2757 TD05
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14
LTC2757 APPLICATIONS INFORMATION
Op Amp Selection Because of the extremely high accuracy of the 18-bit LTC2757, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. Fortunately, the sensitivity of INL and DNL to op amp offset has been greatly reduced compared to previous generations of multiplying DACs. Tables 3 and 4 contain equations for evaluating the effects of op amp parameters on the LTC2757's accuracy. These are the changes the op amp can cause to the INL, DNL, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error.
Table 3. Coefficients for the Equations of Table 4
OUTPUT RANGE 5V 10V 5V 10V 2.5V -2.5V to 7.5V A1 1.1 2.2 2 4 1 1.9 A2 2 3 2 4 1 3 A3 1 0.5 1 0.83 1.4 0.7 1 1 1 0.5 A4 A5 1 1.5 1.5 2.5 1 1.5
Table 4. Easy-to-Use Equations Determine Op Amp Effects on DAC Accuracy in All Output Ranges (Circuit of Page 1). Subscript 1 Refers to Output Amp, Subscript 2 Refers to Reference Inverting Amp.
OP AMP VOS1 (mV) IB1 (nA) AVOL1 (V/mV) VOS2 (mV) IB2 (nA) AVOL2 (V/mV) INL (LSB) 5V V REF DNL (LSB) 5V VOS1 *3.1* VREF UNIPOLAR OFFSET (LSB) A3*VOS1 *52.4* BIPOLAR ZERO ERROR (LSB) UNIPOLAR GAIN ERROR (LSB) VOS1 *52.4* 5V V REF 5V V REF BIPOLAR GAIN ERROR (LSB) VOS1 *52.4* 5V V REF 5V V REF
VOS1*12.1*
5V A3*VOS1 *78.6* 5V V V REF REF IB1*0.524* 5V V REF
IB1*0.0012*
5V I *0.00032* 5V V B1 V REF REF A2* 6 A VOL1 0
IB1*0.524*
5V V REF
IB1*0.0072*
IB1*0.0072*
66 A1* A VOL1 0
0
0
A5* 524 A VOL1 5V V *104.8* 5V V OS2 V REF REF 5V V REF IB2 *1.048* 5V V REF
A5* 524 A VOL1 VOS2 *104.8* 5V V REF
0
A4*VOS2*52.4*
0
0
0
A4*IB2 *0.524*
IB2 *1.048*
5V V REF
0
0
0
262 A4* A VOL2
524 A VOL2
524 A VOL2
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15
LTC2757 APPLICATIONS INFORMATION
Table 5. Partial List of LTC Precision Amplifiers Recommended for Use with the LTC2757 with Relevant Specifications
AMPLIFIER SPECIFICATIONS VOS V 10 25 25 50 75 IB nA 0.05 2 0.1 0.35 10 A VOL V/mV 5600 800 2000 2500 5000 VOLTAGE NOISE nV/Hz 90 10 14 14 5 CURRENT NOISE pA/Hz 0.0018 0.12 0.02 0.008 0.6 SLEW RATE V/s 3 0.25 0.2 0.2 22 GAIN BANDWIDTH PRODUCT MHz 2.5 0.8 1 0.7 90 tSETTLING with LTC2757 s 10ms 120 120 120 2.1 POWER DISSIPATION mW 24 46 11.4 11 117
AMPLIFIER LTC1150 LT1001 LT1012 LT1097 LT1468
Table 5 contains a partial list of LTC precision op amps recommended for use with the LTC2757. The easy-to-use design equations simplify the selection of op amps to meet the system's specified error budget. Select the amplifier from Table 5 and insert the specified op amp parameters in Table 4. Add up all the errors for each category to determine the effect the op amp has on the accuracy of the part. Arithmetic summation gives an (unlikely) worst-case effect. A root-sum-square (RMS) summation produces a more realistic estimate. Op amp offset contributes mostly to DAC output offset and gain error, and has minimal effect on INL and DNL. For example, consider the LTC2757 in unipolar 5V output range. (Note that for this example, the LSB size is 19V.) An op amp offset of 35V will cause 1.8LSB of output offset, and 1.8LSB of gain error; but 0.4LSB of INL, and just 0.1LSB of DNL. While not directly addressed by the simple equations in Tables 3 and 4, temperature effects can be handled just as easily for unipolar and bipolar applications. First, consult an op amp's data sheet to find the worst-case VOS and IB over temperature. Then, plug these numbers in the VOS and IB equations from Table 4 and calculate the temperature-induced effects. For applications where fast settling time is important, Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, offers a thorough discussion of 18-bit DAC settling time and op amp selection.
Recommendations To achieve the full specified static and dynamic performance of the LTC2757, the LT1468 amplifier is recommended; it offers a unique combination of fast settling and excellent DC precision. When using the LT1468 as an output amp, however, the offset voltage (75V max) must be nulled to avoid degrading the linearity of the LTC2757. The LT1468 datasheet shows how to do this with a digital potentiometer. For DC or low-frequency applications, the LTC1150 is the simplest 18-bit accurate output amplifier. An auto-zero amp, its exceptionally low offset (10V max) and offset drift (0.01V/C) make nulling unnecessary. Note: for swings above 8V, use an LT1010 buffer to boost the load current capability of the LTC1150. The settling of auto-zero amps is a special case; see Application Note 120, 1ppm Settling Time Measurement for a Monolithic 18-Bit DAC, Appendix E, for details. The LT1012 and LT1001 are good intermediate output-amp solutions that achieve moderate speed and good accuracy. They are also excellent choices for the reference inverting amplifier in fixed-reference applications. Figure 3 shows a composite output amplifier that achieves fast settling (8s) and very low offset (3V max) without offset nulling. This circuit offers high open-loop gain (1000V/mV min), low input bias current (0.15nA max), fast slew rate (25V/s min), and a high gain-bandwidth product (30MHz typ). The high speed path consists of an LTC6240, which is an 18MHz ultra-low bias current amplifier, followed by an LT1360, a 50MHz fast-slewing amplifier which provides additional gain and the ability to
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16
LTC2757 APPLICATIONS INFORMATION
swing to 10V at the output. Compensation is taken from the output of the LTC6240, allowing the use of a much larger compensation capacitor than if taken after the gain-of-five stage. An LTC2054 auto-zero amplifier senses the voltage at IOUT1 and drives the non-inverting input of the LTC6240 to eliminate the offset of the high speed path. The 100:1 attenuator and input filter reduce the low frequency noise in this stage while maintaining low DC offset. Precision Voltage Reference Considerations Much in the same way selecting an operational amplifier for use with the LTC2757 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. The output voltage of the LTC2757 is directly affected by the voltage reference; thus, any voltage reference error will appear as a DAC output voltage error. There are three primary error sources to consider when selecting a precision voltage reference for 18-bit applications: output voltage initial tolerance, output voltage temperature coefficient and output voltage noise. Initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. Choosing a reference with low output voltage initial tolerance, like the LT1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. A reference's output voltage temperature coefficient affects not only the full-scale error, but can also affect the circuit's INL and DNL performance. If a reference is chosen with a loose output voltage temperature coefficient, then the DAC output voltage along its transfer characteristic will be very dependent on ambient conditions. Minimizing the error due to reference temperature coefficient can be achieved by choosing a precision reference with a low output voltage temperature coefficient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. As precision DAC applications move to 18-bit performance, reference output voltage noise may contribute a dominant share of the system's noise floor. This in turn can degrade system dynamic range and signal-to-noise ratio. Care should be exercised in selecting a voltage reference with as low an output noise voltage as practical for the system resolution desired. Precision voltage references like the LT1236 produce low output noise in the 0.1Hz to 10Hz region, well below the 18-bit LSB level in 5V or 10V fullscale systems. However, as the circuit bandwidths increase, filtering the output of the reference may be required to minimize output noise.
Table 6. Partial List of LTC Precision References Recommended for Use with the LTC2757 with Relevant Specifications
REFERENCE LT1019A-5, LT1019A-10 LT1236A-5, LT1236A-10 LT1460A-5, LT1460A-10 LT1790A-2.5 LTC6655-2.5 LTC6655-5 INITIAL TOLERANCE 0.05% Max 0.05% Max 0.075% Max 0.05% Max 0.025% Max TEMPERATURE DRIFT 5ppm/C Max 5ppm/C Max 10ppm/C Max 10ppm/C Max 2ppm/C Max 0.1Hz to 10Hz NOISE 12VP-P 3VP-P 20VP-P 12VP-P 0.62VP-P
Grounding As with any high-resolution converter, clean grounding is important. A low-impedance analog ground plane is necessary, as are star grounding techniques. Keep the board layer used for star ground continuous to minimize ground resistances; that is, use the star-ground concept without using separate star traces. The IOUT2 pins are of particular concern; INL will be degraded by the code-dependent currents carried by the IOUT2F and IOUT2S pins if voltage drops to ground are allowed to develop. The best strategy here is to tie the pins to the star ground plane by multiple vias located directly underneath the part. Alternatively, the pins may be routed to the star ground point if necessary; join them together at the part and route a single trace of no more than 30 squares of 1oz copper. In the rare case in which neither of these alternatives is practicable, a force/sense amplifier should be used as a ground buffer (see the Typical Applications section). Note, however, that the voltage offset of the ground buffer amp directly contributes to the effects on accuracy specified in Table 4 under `VOS1'. The combined effects of the offsets can be calculated by substituting the total offset from IOUT1 to IOUT2S for VOS1 in the equations.
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17
LTC2757 TYPICAL APPLICATIONS
ALTERNATE AMPLIFIER FOR OPTIMUM SETTLING TIME PERFORMANCE IOUT2S 5 200 200 1000pF 3 IOUT2F 6 1 REF 5V 5 ZETEX* BAT54S U2 LT1012 7 C2 150pF 45, 46 REF R2 43, 44 ROFS 2 3 6 LT1012 3 IOUT2S 5 2
2
IOUT2F ZETEX BAT54S
6 1
6
LT1468
2
3
+ -
6 GEADJ 1, 2 RIN 48 R1
*SCHOTTKY BARRIER DIODE 41, 42 RFB
47 RCOM
C1 27pF 15V 0.1F 8
WR UPD READ D/S CLR
36 35 34 33 20 21
WR UPD READ D/S CLR M-SPAN
LTC2757 18-BIT DAC WITH SPAN SELECT
GND 3 3, 37, 38 SPAN I/O S2-S0 16 VOSADJ 8-16, 23-31 DATA I/O D17-D0 39 VOSADJ VDD
2757 F02
4, 7 17
5V C3 0.1F
FOR MULTIPLYING APPLICATIONS, U2 = LT1468 AND C2 = 15pF
Figure 2. Basic Connections for SoftSpan VOUT DAC with Two Optional Circuits for Driving IOUT2 from GND with a Force/Sense Amplifier
18
+
IOUT2 5, 6
3
-
IOUT1 40
2
U1 LT1468 0.1F
4 -15V
- +
- +
1
VOUT
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LTC2757 PACKAGE DESCRIPTION
LX Package 48-Lead Plastic LQFP (7mm x 7mm)
(Reference LTC DWG # 05-08-1760 Rev O)
7.15 - 7.25 5.50 REF 48 9.00 BSC 7.00 BSC
0.50 BSC
1 2
48
1 2
SEE NOTE: 4
9.00 BSC 5.50 REF 0.20 - 0.30 7.15 - 7.25 A A 7.00 BSC
PACKAGE OUTLINE C0.30 - 0.50
1.30 MIN RECOMMENDED SOLDER PAD LAYOUT APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 1.60 1.35 - 1.45 MAX R0.08 - 0.20
GAUGE PLANE 0.25 0 - 7
11 - 13
11 - 13
1.00 REF 0.45 - 0.75 SECTION A - A
0.09 - 0.20
0.50 BSC
0.17 - 0.27
0.05 - 0.15
LX48 LQFP 0907 REVO
NOTE: 1. PACKAGE DIMENSIONS CONFORM TO JEDEC #MS-026 PACKAGE OUTLINE 2. DIMENSIONS ARE IN MILLIMETERS 3. DIMENSIONS OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.25mm ON ANY SIDE, IF PRESENT
4. PIN-1 INDENTIFIER IS A MOLDED INDENTATION, 0.50mm DIAMETER 5. DRAWING IS NOT TO SCALE
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Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LTC2757 TYPICAL APPLICATION
12V IN 0.1F LTC6655-5 OUT 10F 15V
+
LT1012
VOUT 1k 10k 10k 1F 5V 5V 100pF 15V LTC6240
-
-15V 100pF
-
1k
-
LTC2054
+
LTC1360
+
-5V
+
VDD GEADJ RIN D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S2 S1 S0 D/S READ UPD WR RIN RCOM REF REF ROFS ROFS RFB RFB -5V 1F 10
-
-15V 5pF 4.02k 1k
IOUT1
IOUT2F LTC2757 IOUT2S
TO MICROCONTROLLER
GND VOSADJ
CLR M-SPAN
GND GND GND
2757 F03
Figure 3. Composite Amplifier Provides 18-Bit Precision and Fast Settling
RELATED PARTS
PART NUMBER LTC1591/ LTC1597 LTC1592 LTC1821 LTC2641/ LTC2642 LTC2704 LTC2751 LTC2753 LTC2754 LTC2755 LT1027 LT1236A-5 LTC1150 LT1468 DESCRIPTION Parallel 14-/16-Bit IOUT Single DAC Serial 16-Bit IOUT Single DAC Parallel 16-Bit VOUT Single DAC Serial 12-/14-/16-Bit Unbuffered VOUT Single DACs Serial 12-/14-/16-Bit VOUT SoftSpan Quad DACs Parallel 12-/14-/16-Bit IOUT SoftSpan Single DAC Parallel 12-/14-/16-Bit IOUT SoftSpan Dual DACs Serial 12-/16-Bit IOUT SoftSpan Quad DACs Parallel 12-/14-/16-Bit IOUT SoftSpan Quad DACs Precision Reference Precision Reference 15V Zero-Drift Op Amp 16-Bit Accurate Op Amp COMMENTS Integrated 4-Quadrant Resistors Software-Selectable (SoftSpan) Ranges, 1LSB INL, DNL, 16-Lead SSOP Package 1LSB INL, DNL, 0V to 10V, 0V to -10V, 10V Output Ranges 1LSB INL, 1LSB DNL, 1s Settling, Tiny MSOP-10, 3mm x 3mm DFN-10 Packages Software-Selectable Ranges, Integrated Amplifiers 1LSB INL, DNL, Software-Selectable Ranges, 5mm x 7mm QFN-38 Package 1LSB INL, DNL, Software-Selectable Ranges, 7mm x 7mm QFN-48 Package 1LSB INL, DNL, Software-Selectable Ranges, 7mm x 8mm QFN-52 Package 1LSB INL, DNL, Software-Selectable Ranges, 9mm x 9mm QFN-64 Package 1ppm/C Maximum Drift 0.05% Maximum Tolerance, 1ppm 0.1Hz to 10Hz Noise 10V Maximum Offset Voltage, 1.8VP-P (0.1Hz to 10Hz) Noise, 0.8mA Supply Current 90MHz GBW, 22V/s Slew Rate
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20 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0410 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2010

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